Method for making a metal-insulator-metal capacitor using plate-through mask techniques
US6723600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Jul 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique. The interconnect and capacitor are then finished using one and only one planarizing (e.g., CMP) step. The result is to form a capacitor and interconnect structure in far fewer steps than conventionally required, which translates…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.