Xian J. Ning
37Patents
14h-index
16Co-inventors
74Inventor score
Filing activity: Dec 23, 1997 → Oct 14, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6611453B2 | Self-aligned cross-point MRAM device with aluminum metallization layers | Electricity | 81 | Expired |
| US6692898B2 | Self-aligned conductive line for cross-point magnetic memory integrated circuits | Electricity | 64 | Expired |
| US6620701B2 | Method of fabricating a metal-insulator-metal (MIM) capacitor | Electricity | 41 | Expired |
| US6709874B2 | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation | Electricity | 37 | Expired |
| US6451667B1 | Self-aligned double-sided vertical MIMcap | Electricity | 36 | Expired |
| US6794262B2 | MIM capacitor structures and fabrication methods in dual-damascene structures | Electricity | 35 | Expired |
| US5865901A | Wafer surface cleaning apparatus and method | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6440753B1 | Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6723600B2 | Method for making a metal-insulator-metal capacitor using plate-through mask techniques | Electricity | 26 | Expired |
| US6979526B2 | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs | Electricity | 22 | Expired |
| US6184134A | Dry process for cleaning residues/polymers after metal etch | Emerging Cross-Sectional Technologies | 20 | Expired |
| US5903343A | Method for detecting under-etched vias | Physics | 19 | Expired |
| US6706588B1 | Method of fabricating an integrated circuit having embedded vertical capacitor | Electricity | 16 | Expired |
| US6815248B2 | Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing | Electricity | 15 | Expired |
| US6780775B2 | Design of lithography alignment and overlay measurement marks on CMP finished damascene surface | Electricity | 14 | Expired |
| US6033984A | Dual damascene with bond pads | Electricity | 11 | Expired |
| US6677635B2 | Stacked MIMCap between Cu dual damascene levels | Electricity | 8 | Expired |
| US7547595B2 | Integration scheme method and structure for transistors using strained silicon | Electricity | 7 | Active |
| US7591659B2 | Method and structure for second spacer formation for strained silicon MOS transistors | Electricity | 6 | Active |
| US6960365B2 | Vertical MIMCap manufacturing method | Electricity | 6 | Expired |
| US7820500B2 | Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon | Electricity | 6 | Active |
| US7015110B2 | Method and structure of manufacturing high capacitance metal on insulator capacitors in copper | Electricity | 6 | Expired |
| US7425488B2 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors | Electricity | 5 | Expired |
| US6750115B1 | Method for generating alignment marks for manufacturing MIM capacitors | Electricity | 4 | Expired |
| US7709336B2 | Metal hard mask method and structure for strained silicon MOS transistors | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.