Stack semiconductor chip package and lead frame
US6724074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Nov 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality of external connection terminals for electrically interconnecting the first and second chips to an external device. Each of the first and second chips has its own common and independent electrode pads, and each of the first and second lead groups has its own common and independent leads. The common leads and the common electrode pads are for address and control signals to and from the first and second chips, and the independent leads and the independent electrode pads are for data input and output to and from the first and second chips. The common leads of the first lead group and the common leads of the second lead group are commonly interconnected to be connected to an identical external connection terminal of the plurality of external connection terminals, and the independent leads of the first lead group and the independent leads of the second lead group are connected to different external connection terminal. The first and second chips are disposed symmetrically with respect to the co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.