Method and apparatus for reduced pin count package connection verification
US6724210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Dec 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2853
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip with a weak driver and comparing the transition rise time with a threshold value. For an I/O with a faulty chip-to-package connection, the rise time is much faster than for an I/O with a completed chip-to-package connection. Additional impedances may also be added to the tester fixturing to increase the sensitivity of the test equipment to the capacitance of the I/O connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.