Patent · US Expired

Bias circuit with voltage and temperature stable operating point

US6724243B2 · kind B2 · utility

7Cited by
6References
29Claims
0Family size

Assignee

Inventor

Key dates

Filing dateJun 6, 2002
Grant dateApr 20, 2004
Priority date—
Expiry dateJun 6, 2022

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03F1/30
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.