Multiplexing digital video out on an accelerated graphics port interface
US6724389B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus to map first graphics pins into second graphics pins. A first plurality of data and command pins corresponding to data and command signals in a first graphics mode is mapped into a second plurality of data and command pins corresponding to data and command signals in a second graphics mode. The first and second graphics modes are supported by a first chipset. The second graphics mode is supported by a second chipset. A detector pin strappable to a logic level to indicate an external graphics card is used in the first graphics mode is mapped into a first pin corresponding to a first signal of the second graphics mode. The first signal is ignored by the second chipset during initialization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.