SRAM array with dynamic voltage for reducing active leakage power
US6724648B2 · kind B2 · utility
81Cited by
5References
35Claims
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Key dates
| Filing date | Apr 5, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.