Method of recovering overerased bits in a memory device
US6724662B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.