Nonvolatile semiconductor memory device having selective multiple-speed operation mode
US6724682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.