Memory card, method for allotting logical address, and method for writing data
US6725322B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 21, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Aug 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Blocks and clusters are brought to correspondence thereby to erase blocks of memory area efficiently. A flash memory has its physical addresses partitioned from address 0h sequentially into blocks each having eight sectors. The data area of logical address starts at address 4Dh, which is set to the starting physical address 50h of the block which is close to the top of data area, and the data area is set sequentially to the following physical addresses. The remaining logical addresses 3D7Dh-3D7Fh are brought back to the top of physical address and set to physical addresses 0h-2h. Consequently, clusters (a cluster has 4 k bytes or 2 k bytes) of data sent from a host unit correspond to blocks of physical addresses, enabling block erasure of the flash memory, whereby the number of times of erasing operation at data writing can be reduced significantly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.