Method and system for speculatively invalidating lines in a cache
US6725337B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.