Shared execution unit in a dual core processor
US6725354B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Mar 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.