Power distribution design method for stacked flip-chip packages
US6727118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.