Patent · US Expired

Method for creating an integrated circuit stage wherein fine and large patterns coexist

US6727179B2 · kind B2 · utility

3Cited by

8References

8Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventor

Simon Deleonibus · Le Pont-de-Claix, FR

Key dates

Filing date	Nov 29, 2002
Grant date	Apr 27, 2004
Priority date	—
Expiry date	Nov 29, 2022

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/95
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Successive use is made of a layer of radiation-sensitive resin at points intended to form wide semi-conductor patterns in a still intact layer, under at least one hard mask, then of a resin sensitive to particle bombardment over fine patterns to be formed in this same layer, which may be juxtaposed to those previously mentioned. The first resin patterns are exposed collectively and rapidly by insolation, while electron bombardment allows fine patterns to be formed with great precision. Another hard mask is deposited before the second resin and forms flanks around the wide patterns, which protect the wide patterns from lateral attacks during etching.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.