Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

US6727539B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ramachandra Divakaruni · Ossining, US
• Ulrike Gruening · Wappingers Falls, US
• Jack A. Mandelman · Stormville, US
• Larry Nesbit · Farmington, US
• Carl Radens · Lagrangeville, US

Key dates

• Filing date: May 16, 2002
• Grant date: Apr 27, 2004
• Expiry date: May 16, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.