APS soft reset circuit for reducing image lag
US6727946B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/76
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor. The active pixel sensor may be implemented with any suitable sensor technology, such as photodiode, photogate, or pinned diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.