Dummy cell structure for 1T1C FeRAM cell array
US6728128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Mar 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered be…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.