Memory array system
US6728156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temporary data storer is used for storing data from the memory cell indicated for refreshing. A data inverter inverts data from the memory cell indicated for refreshing. A comparator associated with the temporary data storer and the data inverter compares data in those devices. An indicator bit is associated with the refresh address counter to indicate whether the data stored in the address indicated by the refresh address counter is inverted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.