Arrangement for reducing layer 3 header data supplied to switching logic on a network switch
US6728246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2000 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/354
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a port filter configured for obtaining and filtering relevant layer 2 and layer 3 information from a received layer 2 frame. Each port filter, upon filtering the relevant layer 2 and layer 3 information from a received layer 2 frame, outputs the relevant layer 2 and layer 3 information to switching logic, enabling the switching logic to perform layer 3 processing to determine a layer 3 switching operation to be performed on the received layer 2 frame. Hence, the switching logic performs the layer 3 processing based on the relevant layer 2 and layer 3 information, without the necessity of parsing the received layer 2 and layer 3 information by the switching logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.