Multiple instantiation system
US6728667B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1998 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Oct 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention features a method of simultaneously conducting simulation testing of a plurality of simulated device designs using cycle-based software which is capable of simultaneously executing a number of simulation tests along separate test pathways for each simulated device. The method is appropriate for situations in which the simulated device designs each comprise essentially identical sequences of boolean instructions. The method contemplates designating a single bit location of a multiple-word memory device for each test of each simulated device. As the test progress, the results of each test are stored in the appropriate designated bit location for such test. This allows a total number of simultaneous tests equal to the number of bits available in the words making up the memory of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.