Method and apparatus for converting non-burst write cycles to burst write cycles across a bus bridge
US6728813B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers which store plural sets of write addresses and data for a system bus, a comparator for deciding whether write addresses in succession forming a continuous write address exist in the write addresses stored in the buffers, and apparatus for converting access corresponding to writing operations for the continuous write addresses into a fixed length burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the comparator 27 decides that write addresses in succession exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.