System and method for tracking and processing parallel coherent memory accesses
US6728843B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses. The system control unit includes a qualifier and a scheduler that assigns each transaction to a particular finite state machine (FSM). Each FSM executes a single transaction until completed. Each FSM machine maintains a record or keeps track of the state of progress of a transaction that is being executed by the system control unit. The FSMs keep track of the data by storing the data, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, for each transaction in a data buffer. The data value corresponding to a particular transaction may be retrieved from the main memory using a FSM. Since a different FSM is used to retrieve data values, the execution of these transactions can be performed in parallel. Parallel processing of memory accesses using FSMs enhances the speed and efficiency of computer systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.