Modified Harvard architecture processor having program memory space mapped to data memory space
US6728856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Apr 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.