Arithmetic built-in self-test of multiple scan-based integrated circuits
US6728901B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Operating logic uses data paths of the processor core to implement the ABIST. In one embodiment, operating logic generates test patterns for the peripheral devices using the data paths of the processor core, loads the test patterns into the parallel scan registers of the peripheral devices, recovers test responses from the parallel scan registers, and compacts responses from the peripheral devices once again using the data paths of the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.