Random path delay testing methodology

US6728914B2 · kind B2 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Kevin William McCauley · Hudson, US
• William V. Huott · Holmes, US
• Mary P. Kusko · Poughkeepsie, US
• Peilin Song · Lagrangeville, US
• Richard F. Rizzolo · Red Hook, US
• Ulrich Baur · Holzgerlingen, DE
• Franco Motika · Hopewell Junction, US

Key dates

• Filing date: Dec 22, 2000
• Grant date: Apr 27, 2004
• Expiry date: Jan 6, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31858
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.