Method of fabricating a drain isolated LDMOS device
US6729886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.