Multi-layer silicide block process
US6730554B1 · kind B1 · utility
15Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125) and an optional patterned silicon oxide layer (135) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (170) during the formation of metal silicide regions (160) on the integrated circuit resistor (170).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.