Semiconductor memory and process for fabricating the same
US6730955B2 · kind B2 · utility
6Cited by
2References
28Claims
0Family size
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Key dates
| Filing date | Mar 18, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.