Semiconductor device
US6730973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
Abstract
A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.