Low voltage differential signaling circuit with mid-point bias
US6731135B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2001 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Nov 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A low voltage differential signaling circuit employs a mid-point biasing scheme that maintains a desired common mode voltage across all logic states signaled by the circuit. In one driver implementation, separate conduction paths are used to signal respective logic states on a pair of differential signal lines. A common pair of resistors are provided in the conduction path between the two signal lines. The midpoint between the pair of resistors is tied to the desired common mode voltage. A midpoint bias circuit is coupled to a variable resistance in the conduction path so as to maintain the desired common mode voltage by virtue of a voltage division so as to minimize the amount of non-conduction path current at the mid point node. In one example, a replica circuit further provides an anticipated midpoint voltage to the midpoint bias circuit for comparison to the desired midpoint voltage. The midpoint bias circuit adjusts the variable resistance in accordance with the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.