Total error multiplier for optimizing read/write channel
US6731443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Apr 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/22
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood (“PRML”) read/write channel is disclosed. A channel margining circuit that is configured to carry out an embodiment for a method of optimizing the bit error rates of a read/write channel is described. The margining circuit derives an interference signal to stress a read/write channel for optimizing the bit error rate. The signal is derived from bit errors inherent with the read/write channel. The circuit reduces the time to optimize the channel by providing an amplified interference signal that increases a bit error rate during optimization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.