Loadless 4T SRAM cell with PMOS drivers
US6731533B2 · kind B2 · utility
14Cited by
6References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between a storage node (230) and a bitline (200). The NMOS transistor is gated by the wordline (190). A PMOS drive transistor (180) is connected between the storage node (230) and a supply voltage (255).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.