Circuit for accurate memory read operations
US6731542B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.