Method and system to process semiconductor wafers
US6732006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Feb 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67276
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system for the processing of one or more wafers in a process tool is provided, the method comprising subjecting the one or more wafer in a reaction chamber to a process, generating an inhibit next load flag on predefined conditions, the inhibit next load flag not effecting already started processing of a wafer. Prior to the start of the processing of a wafer, a check is performed to see if an inhibit next load flag has been set. When upon checking it has been found that an inhibit next load has been set, the start of the process in the reaction chamber is prohibited. The method further includes providing pre-programmed recovery procedures, such that after execution of a pre-programmed recovery procedure the to be processed wafer of which the start of the processing is prohibited ends in a defined state such that the tool can be used for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.