Processor having a conditional branch extension of an instruction set architecture
US6732259B1 · kind B1 · utility
16Cited by
71References
78Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.