Method for forming a wafer level chip scale package, and package formed thereby
US6732913B2 · kind B2 · utility
55Cited by
6References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a chip scale package is described. The method utilizes wafer level processes to obtain a chip level package. The method particularly avoids the use of mechanical grinding by the novel use of molding, extruding, and etching technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.