Semiconductor chip grid array package design and method of manufacture
US6734039B2 · kind B2 · utility
23Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.