Semiconductor integrated circuit device and process for manufacturing
US6734060B2 · kind B2 · utility
8Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1998 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a peripheral circuit region of a DRAM, two connection holes 17a, 17b for connecting a first layer line 14 and a second layer line 26 electrically are opened separately in two processes. After forming the connection holes 17a and 17b, plugs 18a and 215a are formed in the connection holes 17a and 17b, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.