Nonvolatile memory cell with high programming efficiency
US6734490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.