Relative timing sequence for reader amplifiers
US6735034B1 · kind B1 · utility
1Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Nov 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2005/0013
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.