Integrated memory using prefetch architecture and method for operating an integrated memory

US6735138B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stephan Schröder · Birkenfeld, DE
• Manfred Dobler · Hersbruck, DE

Key dates

• Filing date: May 28, 2003
• Grant date: May 11, 2004
• Expiry date: May 28, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/2254
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.