System and method for providing asynchronous SRAM functionality with a DRAM array
US6735139B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Dec 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system 100 which provides asynchronous SRAM functionality with a DRAM device. The system 100 includes an address transition detector circuit 102, a memory clock generator circuit 104, a refresh timer 106, a refresh address counter 108, a memory access controller 110, a memory control sequencer 112, an address buffer 114, a write data buffer 116, a three-input address multiplexer 118, a two-input data multiplexer 120, inverters 122, 124, 126, and 128, AND gates 130, 132, and 134, NOR gates 136, 138, 140, and 142, OR gate 156, and a DRAM array 144 of memory cells. The components of system 100 cooperate to selectively interrupt external memory commands, such as read and write commands, in order to perform refresh operations on array 144.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.