Method and apparatus for testing, characterizing and tuning a chip interface

US6735543B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Steven M. Douskey · Rochester, US
• Daniel M. Dreps · Georgetown, US
• Frank D. Ferraiolo · New Windsor, US
• Curtis Walter Preuss · Rochester, US
• Robert J. Reese · Austin, US
• Paul Rudrud · Rochester, US
• James Donald Ryan · Rochester, US
• Robert R. Williams · Allen, US

Key dates

• Filing date: Nov 29, 2001
• Grant date: May 11, 2004
• Expiry date: Mar 6, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318385
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.