Process for making fine pitch connections between devices and structure made by the process
US6737297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Aug 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.