Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect
US6737326B2 · kind B2 · utility
6Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | May 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/474
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.