Semiconductor device isolation structure and method of forming
US6737333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.