Shallow trench isolation type semiconductor device and method of manufacturing the same
US6737335B2 · kind B2 · utility
12Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2003 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | May 19, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.