Composite spacer scheme with low overlapped parasitic capacitance
US6737342B1 · kind B1 · utility
7Cited by
15References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jun 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.