Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
US6737347B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Sep 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections. The portion of the conductive material remaining in each recess is self-aligned to be immediately adjacent at least one gate section, and serves as a local interconnect for a respective source or drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.