Thick thermal oxide layers and isolation regions in a silicon-containing substrate for high voltage applications
US6737355B2 · kind B2 · utility
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30Claims
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Assignee
Inventor
Key dates
| Filing date | Dec 6, 2001 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of forming a thick silicon oxide layer upon or internal to a silicon structure. The method is particularly useful in creating isolation regions within a silicon-containing structure, where such isolation regions can withstand high voltages. The electrically isolating thick silicon oxide layer or isolation regions can be shaped, machined, or etched to provide feedthroughs for vertical or horizontal interconnects. The feedthroughs may be coated with metal or filled with metal to provide the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.